The first details on Intel’s Arrow Lake processors are revealed

Recent leaks have shed light on Intel’s upcoming desktop processor platform, codenamed Arrow Lake. This platform, designated as Core Ultra 200, will succeed the current generation. And is expected to utilize the LGA 1851 socket alongside UDIMM memory.

Intel Unveils Details of Next-Gen Desktop Processors: Core Ultra 200 (Arrow Lake)


The leaks revealed details of two potential configurations within the Core Ultra 200 family:

  • A 24-core variant
  • A 20-core variant

It’s important to note that these early engineering samples lack hyperthreading technology and currently operate at a base clock speed of 2.3 GHz, which is typical for pre-release models. Final retail versions will likely boast higher clock speeds. Additionally, the official retail names and partnerships with motherboard manufacturers remain undisclosed.

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While core count seems to mirror the current Raptor Lake generation (8 performance cores and 16 efficiency cores), the leaks suggest significant advancements in the efficiency core architecture (LP-cores). This could lead to improved performance and power efficiency.

The company hasn’t confirmed a launch date for the Core Ultra 200 platform. However, the recent announcement of the LGA 1851 socket, compatible with the Meteor Lake-PS processors for embedded systems, suggests its potential use with Core Ultra 200 and future consumer-oriented processors.

Rumors, though unconfirmed, hint at the possibility of an Xe-LPG graphics processing unit (GPU) architecture based on the Alchemist architecture for the desktop Core Ultra 200 series. Mobile processors (H-Series) might utilize an upgraded version, Xe-LPG +, but specifics regarding the GPU architecture remain unclear.

With these leaks, we gain a glimpse into the potential features of Intel’s next-generation desktop processor platform. While details like final clock speeds, official names, and specific functionalities are yet to be revealed, the Core Ultra 200 (Arrow Lake) promises advancements in core architecture and potentially improved performance and efficiency.

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Via: gizchina.com

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